Title :
Vertical In0.7Ga0.3As nanowire surrounding-gate transistors with high-k gate dielectric on Si substrate
Author :
Tomioka, Katsuhiro ; Yoshimura, Masatoshi ; Fukui, Takashi
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
In this paper, direct integration of vertical InGaAs nanowires (NWs) on Si substrate without buffering techniques, and fabrication of InGaAs NW surrounding-gate transistors (SGTs) with high-k gate dielectrics is reported for the first time. Furthermore, we investigated a passivation technique using InGaAs/InP/InAlAs/InGaAs core-multishell (CMS) structure, and showed enhancement of transconductance (Gm) and ION/IOFF ratio of the InGaAs CMS NW-SGT. The peak Gm for the InGaAs-related CMS NW-SGT was 500 μS/μm at VDS of 1.00V, and ION/IOFF ratio was ~ 109.
Keywords :
III-V semiconductors; aluminium compounds; field effect transistors; gallium arsenide; high-k dielectric thin films; indium compounds; nanowires; passivation; InGaAs-InP-InAlAs-InGaAs; Si; Si substrate; core-multishell structure; direct integration; high-k gate dielectric; passivation technique; vertical InGaAs nanowires; vertical nanowire surrounding-gate transistors; voltage 1 V; Indium gallium arsenide; Indium phosphide; Logic gates; Silicon; Substrates; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131663
