Compact capacitance and capacitive coupling-noise modeling of Through-Oxide Vias in FDSOI based ultra-high density 3-D ICs

Fully-Depleted SOI (FDSOI) technology boosts the opportunity to make 3-D ICs with ultra-high integration density, due to the short and tiny Through-Oxide Vias (TOVs), which are made after removing the entire silicon under the buried-oxide layer. This work, for the first time, develops compact physical models for the capacitance of the TOV and the coupling capacitance between TOV and active regions in presence of periodical power lines, from fundamental electrostatic considerations. Calculation results from the models show good agreement with the simulation results from a full-3D capacitance solver. The models are further used to analyze the threshold voltage (V_th) variation in the FDSOI MOSFETs. The TOV in FDSOI and the Through-Silicon Via (TSV) in bulk CMOS based 3-D ICs are finally compared in terms of the self impedance as well as their impact on MOSFET V_th variation through capacitive-noise coupling. These results provide important insights to TOV/TSV design and optimization in emerging 3-D ICs.