Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA

Author

Kleines, H. ; Wustner, P. ; Drochner, M. ; Ackens, A. ; Erven, W. ; Kammerling, P. ; Ramm, M. ; van Waasen, S.

Author_Institution

Zentralinst. fur Elektron., Forschungszentrum Julich, Julich, Germany

fYear

2012

fDate

9-15 June 2012

Firstpage

1

Lastpage

3

Abstract

In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.

Keywords

field programmable gate arrays; nuclear electronics; optical computing; optical design techniques; optical logic; optical sensors; optical transceivers; peripheral interfaces; protocols; proton detection; FPGA; MicroTCA; PANDA detector system; PCIe; X2 transceivers; Xilinx Virtex 5; link protocol; optical uplink; Backplanes; Data acquisition; Detectors; Field programmable gate arrays; Optical fiber communication; Transceivers; Uplink;

fLanguage

English

Publisher

ieee

Conference_Titel

Real Time Conference (RT), 2012 18th IEEE-NPSS

Conference_Location

Berkeley, CA

Print_ISBN

978-1-4673-1082-6

Type

conf

DOI

10.1109/RTC.2012.6418149

Filename

6418149