An FPGA-based readout module for the DAQ subsystem of the DSSC detector at the European XFEL

The DSSC collaboration is developing an instrument to detect synchrotron X-rays (E >; 0.5 keV) at the European XFEL. The DEPFET-based sensors with integrated signal compression will be read out by 16 ASICs per sensor module. During the XFEL bursts (600 μs), data are acquired at a rate of up to 4.5MHz, and subsequently read out during the 99.4 ms long burst gaps. Two detector specific, FPGA-based modules, the I/O Board (IOB, Spartan-6), and the Patch Panel Transceiver (PPT, Kintex-7), form the DAQ readout chain of the DSSC detector. Each of the 16 sensor modules is provided with an IOB in close proximity to the sensors. An IOB concentrates the ASIC data into four serial 3.125 Gb/s data links. It also performs several controlling tasks, such as switching the sensor voltages for minimizing power consumption during the readout phase. A PPT serves as a master to the four IOBs of one detector quadrant. It receives the timing and control information from the XFEL timing system, and delivers DSSC specific control commands to the IOBs, and readout ASICs. It also concentrates the 16 × 3.125 Gb/s links of four IOBs (payload data rate ≈ 1.1 Gb/s per link) into four 10 Gb/s optical SFP+ links (QSFP+), which connect to the central XFEL DAQ system. We present the implementation of the IOB / PPT prototyping FPGA firmware, and the test environment.