Design of a family of VLSI high speed fuzzy processors

This paper describes the architecture of two VLSI Fuzzy chips designed to run at very high speed: 50 Mega Fuzzy Inference per Second (MFIPS) at least. The two projects differ in the number of inputs; one processes 2-4 seven bit inputs while the other one 8-16 seven bit inputs. The two chips have been designed for applications in High Energy Physics Experiments (HEPE) where the apparatus, called trigger device, needs to discriminate different nuclear events in few microseconds. So far most of the fuzzy logic applications do not require high speed because not required by the industrial applications, therefore they have been done by implementing the fuzzy system on microprocessors, DSPs, or on commercial fuzzy chips which do not have very high speed performances like those necessary for HEPE. In the first phase of our research 1.0 μm VLSI fuzzy chip a prototype with four 7 bit inputs and one output running at 50 MFIPS was designed and constructed whose processing rate depends upon the number of rules of the fuzzy system. To further increase the speed we have faced the problem of processing, when possible, only the active fuzzy rules which are a few percent of the total ones