Fault modeling for FinFET circuits

FinFETs are expected to supplant planar CMOS field-effect transistors (FETs) in the near future, owing to their superior electrical characteristics. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all defects in FinFET circuits. In this work, we address the above problem using mixed-mode Sentaurus TCAD device simulations and demonstrate that while faults defined for planar MOSFETs show significant overlaps with FinFETs, they are insufficient to encompass all regimes of operation. Results indicate that new fault models are needed to adequately capture the behavior of logic gates based on independent-gate FinFETs with opens on the back gate, and shorted-gate FinFETs which have been accidentally etched into independent-gate structures.