Title :
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
Author :
Jabeur, K. ; Navarro, D. ; O´Connor, I. ; Gaillardon, P.E. ; Ben Jamaa, M.H. ; Clermidy, F.
Author_Institution :
Lyon Inst. of Nanotechnol., Univ. of Lyon, Ecully, France
Abstract :
This paper presents a set of circuit design approaches to achieve clocked standard logic cell functions with ambipolar double-gate devices such as the Double Gate Carbon Nanotube FET (DG-CNTFET). The cells presented in this work use the infield controllability of the device to reduce transistor count over conventional standard cells by only requiring n+1 transistors (where n is the fan-in), and achieve improved time delay by a factor of 2 for comparable power consumption.
Keywords :
carbon nanotubes; field effect transistors; logic circuits; network synthesis; ambipolar double-gate FET; circuit design; clocked standard cells; double gate carbon nanotube FET; logic cell functions; transistor count; CNTFETs; Circuit synthesis; Clocks; Controllability; Delay effects; Double-gate FETs; Energy consumption; Logic circuits; Logic design; Logic devices; CNTFETs; advanced technologies; ambipolar double-gate devices; dynamic logic; standard cells;
Conference_Titel :
Nanoscale Architectures (NANOARCH), 2010 IEEE/ACM International Symposium on
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4244-8020-3
DOI :
10.1109/NANOARCH.2010.5510928
