The design of a modulo scheduler for a superscalar RISC processor

Module scheduling is a form of software pipelining that extracts parallelism from inner loops by overlapping the execution of successive iterations. This paper describes the design of a commercial module scheduler for a modern superscalar RISC processor. Systematic amortization of instructions and partitioned dependence graph scheduling deliver good performance in the face of limited instruction issue. Slot reservation prior to scheduling permits effective handling of both pipelined and non-pipelined instructions. Constraining the dependence graph allows loops containing simple control flow to be scheduled with very limited architectural support. A virtual register allocation phase during scheduling uses simple but effective heuristics to control high register pressure. Extensive data on the performance of the module scheduler on a collection of over one thousand loops are presented