Design optimization of a practical ESD protection circuit by CAD: a case study

Author

Wang, Albert Z. ; Tsay, Chen H. ; Bielawski, John ; DeClue, Larry

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

fYear

1999

fDate

1999

Firstpage

116

Lastpage

119

Abstract

This paper reports design optimization of a practical ESD protection circuit by ESD simulation. A compact ESD protection structure was designed for a transceiver chip. Chip malfunction was observed in tests. ESD simulation and measurement measures showed the malfunction was caused by large substrate current induced early-triggering of the ESD devices. Solutions were provided to optimize the chip. It shows that ESD simulation is a powerful means in conducting practical ESD protection designs

Keywords

BiCMOS integrated circuits; circuit CAD; circuit optimisation; electrostatic discharge; integrated circuit design; integrated circuit reliability; integrated circuit testing; mixed analogue-digital integrated circuits; protection; transceivers; CAD; ESD protection circuit; ESD simulation; case study; chip malfunction; design optimization; early-triggering; large substrate current; mixed-mode ESD simulation; submicron BiCMOS process; tests; transceiver chip; Circuit simulation; Computer aided software engineering; Design automation; Design optimization; Electrostatic discharge; Pins; Protection; Semiconductor device measurement; Testing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1999. Proceedings of the Thirteenth Biennial

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-5240-8

Type

conf

DOI

10.1109/UGIM.1999.782835

Filename

782835