An assignment algorithm for reconfiguration of fault tolerant linear array

Author

Chen, Chang ; Kakuda, Yoshiaki ; Kikuno, Tohru

Author_Institution

Dept. of Inf. & Comput. Sci., Osaka Univ., Osaka, Japan

fYear

1992

fDate

1-3 April 1992

Firstpage

440

Lastpage

447

Abstract

A new technique for reconfiguration of a fault-tolerant linear array that is constructed by connecting multiple modular redundant processors is proposed. The array has the following characteristics: a fault of any copy of each processor can be masked without the need for reconfiguration, and the array can be efficiently reconfigured for maximizing the capability to detect and correct any future faults when some voters and copies of processors fail. The reconfiguration problem for the array is formalized, and a linear time algorithm for the reconfiguration is proposed. An extension of the reconfiguration problem and its algorithm are discussed.<>

Keywords

fault tolerant computing; systolic arrays; assignment algorithm; fault tolerant linear array; faults correction; faults detection; linear time algorithm; multiple modular redundant processors; reconfiguration; Computer architecture; Error correction; Fault detection; Fault tolerance; Fault tolerant systems; Joining processes; Nuclear magnetic resonance; Switches; Systolic arrays; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Communications, 1992. Conference Proceedings., Eleventh Annual International Phoenix Conference on

Conference_Location

Scottsdale, AZ, USA

Print_ISBN

0-7803-0605-8

Type

conf

DOI

10.1109/PCCC.1992.200589

Filename

200589