Title :
Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell
Author :
Ahn, J.H. ; Park, Y.W. ; Shin, J.H. ; Kim, S.T. ; Shim, S.P. ; Nam, S.W. ; Park, W.M. ; Shin, H.B. ; Choi, C.S. ; Kim, K.T. ; Chin, D. ; Kwon, O.H. ; Hwang, C.G.
Author_Institution :
Samsung Electronics, Kyungki-Do, South Korea
Abstract :
Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<>
Keywords :
DRAM chips; VLSI; etching; 256 Mbit; 30 fF; DRAM stack cell; MVP technology; additional Fin undercut structure; anisotropic dry etch; etch mask; hemispherical grain; maximized cell capacitance; micro villus patterning technology; oxide layer; oxide wet etchant; physical stability; storage electrode; Anisotropic magnetoresistance; Bars; Capacitance; Capacitors; Dry etching; Electric breakdown; Electrodes; Random access memory; Surface treatment; Wet etching;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200619
