DocumentCode :
3042024
Title :
Using decision diagrams to compactly represent the state space for explicit model checking
Author :
Hao Zheng ; Price, Aaron ; Myers, Cory
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
2012
fDate :
9-10 Nov. 2012
Firstpage :
17
Lastpage :
24
Abstract :
The enormous number of states reachable during explicit model checking is the main bottleneck for scalability. This paper presents approaches of using decision diagrams to represent very large state space compactly and efficiently. This is possible for asynchronous systems as two system states connected by a transition often share many same local portions. Using decision diagrams can significantly reduce memory demand by not using memory to store the redundant information among different states. This paper considers multi-value decision diagrams for this purpose. Additionally, a technique to reduce the runtime overhead of using these diagrams is also described. Experimental results and comparison with the state compression method as implemented in the model checker SPIN show that the approaches presented in this paper are memory efficient for storing large state space with acceptable runtime overhead.
Keywords :
decision diagrams; formal verification; asynchronous systems; explicit model checking; model checker SPIN; multivalue decision diagrams; runtime overhead reduction; state space representation; Boolean functions; Data structures; Decision trees; Grammar; Model checking; Nickel; Reachability analysis; decision diagrams; formal verification; model checking; state compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location :
Huntington Beach, CA
ISSN :
1552-6674
Print_ISBN :
978-1-4673-2897-5
Type :
conf
DOI :
10.1109/HLDVT.2012.6418238
Filename :
6418238
Link To Document :
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