Title :
Constrained signal selection for post-silicon validation
Author :
Basu, Kaustav ; Mishra, P. ; Patra, Prabir
Author_Institution :
Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA
Abstract :
Limited signal observability is a major concern during post-silicon validation. On-chip trace buffers store a small number of signal states every cycle. Existing signal selection techniques are designed to select a set of signals based on the trace buffer width. In a real-life scenario, it is reasonable that a designer has determined some important signals that must be traced. In this paper, we study the constrained signal selection problem where a set of trace signals are already provided by the designer and the remaining signals have to be determined to improve overall restoration performance. Our experimental results using ISCAS´89 benchmarks demonstrate that up to 5% improvement can be obtained in restoration performance compared to existing approaches.
Keywords :
logic testing; system-on-chip; constrained signal selection; on-chip trace buffer; post-silicon validation; signal observability; signal selection technique; trace buffer width; Algorithm design and analysis; Benchmark testing; Design automation; Logic gates; Observability; Silicon; System-on-a-chip;
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE International
Conference_Location :
Huntington Beach, CA
Print_ISBN :
978-1-4673-2897-5
DOI :
10.1109/HLDVT.2012.6418245