Constant Capacitance Deep-Level Transient Spectroscopy Study of Bulk Traps and Interface States in P Implanted Si MOS Capacitors

Author

Villis, B.J. ; McCallum, J.C. ; Lay, M.D.H. ; Gauja, E.

Author_Institution

Sch. of Phys., Melbourne Univ., Carlton, Vic.

fYear

2004

fDate

8-10 Dec. 2004

Firstpage

113

Lastpage

116

Abstract

Constant capacitance deep-level transient spectroscopy (CC-DLTS) has been used to study bulk traps and interface states in Si metal-oxide semiconductor (MOS) capacitors with 50 nm thick thermally-grown oxides on an n-type substrate. Both as-grown and P-implanted samples were studied. The P implants were performed at 50 keV to a dose of 1 × 10 ¹⁰ cm^-2. Thermal anneals in the temperature range 200-400°C were performed on implanted and as-grown samples to examine the dynamics of trap annealing

Keywords

MOS capacitors; annealing; deep level transient spectroscopy; elemental semiconductors; interface states; ion implantation; phosphorus; silicon; 50 keV; 50 nm; P implantation; Si metal-oxide semiconductor capacitors; Si:P; bulk traps; constant capacitance deep-level transient spectroscopy; interface states; thermal annealing; trap annealing; Australia; Capacitance; Interface states; MOS capacitors; Physics; Quantum computing; Rapid thermal annealing; Spectroscopy; Temperature distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Optoelectronic and Microelectronic Materials and Devices, 2004 Conference on

Conference_Location

Brisbane, Qld.

Print_ISBN

0-7803-8820-8

Type

conf

DOI

10.1109/COMMAD.2004.1577505

Filename

1577505