Title :
Modeling the Effects of Interface Traps on Scanning Capacitance Microscopy dC/dV Measurement
Author :
Hong, Y.D. ; Yeow, Y.T.
Author_Institution :
Sch. of Information Technol. & Electr. Eng., Queensland Univ., Brisbane, Qld.
Abstract :
Scanning capacitance microscopy (SCM) measurement is a proposed tool for dopant profile extraction for semiconductor material. The influence of interface traps on SCM dC/dV data is still unclear. In this paper we report on the simulation work used to study the nature of SCM dC/dV data in the presence of interface traps. A technique to correctly simulate dC/dV of SCM measurement is then presented based on our justification. We also analyze how charge of interface traps surrounding SCM probe would affect SCM dC/dV due the small SCM probe dimension
Keywords :
capacitance measurement; doping profiles; interface states; scanning probe microscopy; dC/dV measurement; dopant profile extraction; interface traps; scanning capacitance microscopy; Capacitance measurement; Capacitance-voltage characteristics; Data mining; Electric variables measurement; MOS capacitors; Microscopy; Physics; Probes; Semiconductor materials; Substrates; SCM; component; interface traps; modeling; scanning capacitance microscpy;
Conference_Titel :
Optoelectronic and Microelectronic Materials and Devices, 2004 Conference on
Conference_Location :
Brisbane, Qld.
Print_ISBN :
0-7803-8820-8
DOI :
10.1109/COMMAD.2004.1577514
