Title :
Parameterized SPICE subcircuits for submicron multilevel interconnect modeling
Author :
Chang, K.-J. ; Oh, S.-Y. ; Chang, N.H. ; Lee, K.
Author_Institution :
Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<>
Keywords :
BiCMOS integrated circuits; SPICE; VLSI; metallisation; semiconductor process modelling; VLSI designers; device modeling; finite difference 2D/3D capacitance simulators; parameterized SPICE subcircuits; submicron BiCMOS process; submicron multilevel interconnect modeling; Capacitance; Circuit simulation; Conductors; Dielectrics and electrical insulation; Equations; Integrated circuit interconnections; Numerical simulation; Polynomials; SPICE; Very large scale integration;
Conference_Titel :
VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0698-8
DOI :
10.1109/VLSIT.1992.200653
