Design considerations for sub-0.35 mu m buried channel P-MOSFET devices

Author

Mazure, A. ; Subrahmanyan, R. ; Gunderson, C. ; Orlowski, M.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1992

fDate

2-4 June 1992

Firstpage

92

Lastpage

93

Abstract

Based on simulation and experimental work it is shown that the most important parameters are the LDD dose and the p/sup +/ source/drain junction depth, not the buried junction channel. It is also shown that buried channels can readily be scaled down to 0.2 mu m geometries by adjusting the source/drain construction. The design considerations presented are confirmed by fabricated 0.25- mu m-gate (L/sub eff/ approximately=0.19 mu m) buried p MOSFETs with off-leakage current below 1 pA/ mu m at V/sub G/=0 V, V/sub DS/=-3.3 V. In addition, it is shown that buried channels can readily be scaled down to 0.2- mu m geometries by adjusting the source/drain parameters while maintaining a reasonably high back-end thermal budget.<>

Keywords

design engineering; insulated gate field effect transistors; leakage currents; 0.2 to 0.35 micron; LDD dose; buried channel pMOSFET; design considerations; high back-end thermal budget; off-leakage current; p/sup +/ source/drain junction depth; Boron; Controllability; Geometry; Implants; Laboratories; MOS devices; MOSFET circuits; Performance analysis; Research and development; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0698-8

Type

conf

DOI

10.1109/VLSIT.1992.200664

Filename

200664