Accurate technology independent models for submicron CMOS and BiCMOS circuits

Two accurate analytical models for the delay evaluation of submicron CMOS and BiCMOS buffers are presented. They are technology independent in the way that they base their validity on a set of process parameters that can be extracted directly from SPICE models or experimental measurements. Both models make use of an accurate delay model for submicron MOS transistors which is presented too. It takes into account a ramp shape input voltage and a feed-forward capacitive coupling between gate and drain contacts, along with the main second order effect present in submicron MOS transistors. Though the calculations are carried out for a buffer case, the models can be applied to the delay study of more general circuits (e.g. for the optimization of high speed logic gates)