Critical hazard free test generation for asynchronous circuits

Author

Khoche, Ajay ; Brunvand, Erik

Author_Institution

Sunrise Test Syst., Fremont, CA, USA

fYear

1997

fDate

27 Apr-1 May 1997

Firstpage

203

Lastpage

208

Abstract

We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator

Keywords

asynchronous circuits; automatic testing; boundary scan testing; delays; discrete Fourier transforms; integrated circuit testing; logic testing; D-algorithm; asynchronous circuits; critical hazard-free tests; macro-module library; partial scan based DFT environment; self-timed control circuits; six-valued algebra; unbounded delay model; Algebra; Asynchronous circuits; Automatic testing; Circuit testing; Clocks; Delay; Hazards; Libraries; Protocols; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1997., 15th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-7810-0

Type

conf

DOI

10.1109/VTEST.1997.600270

Filename

600270

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3042696