A fast matrix-based approach to the computation of valid masking patterns for HSLC non-binary counters

HSLC counters are very high-speed non-binary counters. These kinds of devices are highly modular, but in order to determine the exact configuration of their architecture the so called masking patterns need to be calculated. A possible solution to this problem consists of explicitly simulating the counter; however, this approach becomes too time consuming when the size of the counter increases. In this paper, we propose a new technique to shorten the masking pattern calculation time by exploiting matrix operations