DocumentCode
3042867
Title
Efficient testing of tree circuits
Author
Blanton, Shawn R. ; Hayes, John P.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
1993
fDate
22-24 June 1993
Firstpage
176
Lastpage
185
Abstract
The authors investigate the testing properties of a class of regular circuits known as trees which include parity circuits, multiplexers, and decoders. Viewing a tree as overlapping one-dimensional arrays makes it possible to extend the testing properties of these arrays to trees. The authors give conditions for individually testing the arrays within a tree with a constant number of tests. Under the best conditions when this can be done, the bound on the number of tests required is proportional to the number of leaf modules in the tree. The authors also present necessary and sufficient conditions for C-testing trees, that is, testing trees of arbitrary size with a constant number of tests. More restrictive conditions are also presented that allow trees to be completely C-tested with the minimum number of tests.
Keywords
logic testing; C-testing trees; decoders; leaf modules; logic circuits testing; multiplexers; necessary and sufficient conditions; overlapping one-dimensional arrays; parity circuits; regular circuits; tree circuits testing; Adders; Circuit testing; Combinational circuits; Computer architecture; Decoding; Laboratories; Logic arrays; Logic testing; Multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
Conference_Location
Toulouse, France
ISSN
0731-3071
Print_ISBN
0-8186-3680-7
Type
conf
DOI
10.1109/FTCS.1993.627321
Filename
627321
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