CoveT: a coverage tracker for collision events in system verification

Hardware escapes in complex ASIC designs are very costly to fix in terms of both money and time. It is therefore necessary for design bugs to be detected and removed as early as possible in the design cycle. One cost-effective way of debugging a design is to simulate a software model of the design. However it has been traditionally difficult to measure how much of the design has been verified and how much simulation is sufficient. In this paper we describe a coverage tool called CoveT that is currently in use for system verification within IBM´s RS/6000 Division. The novel idea behind this tool is the area of focus chosen for coverage measurement, viz., concurrent occurrence of multiple events at a given unit that tend to stress the underlying state machines. Our tool is helping us to track the progress of system simulation, uncover areas that are insufficiently stressed, potentially expose complex bugs, and increase the effectiveness of simulation cycles