• DocumentCode
    3043009
  • Title

    Using speculation to simplify multiprocessor design

  • Author

    Sorin, Daniel J. ; Martin, Milo M K ; Hill, Mark D. ; Wood, David A.

  • Author_Institution
    Dept. of Elec. & Comp. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2004
  • fDate
    26-30 April 2004
  • Firstpage
    75
  • Abstract
    Summary form only given. Modern multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that rare corner-case events behave correctly. We propose using "speculation for simplicity " to enable designers to focus on common-case scenarios. Our approach is to speculate that rare events will not occur and rely on an efficient recovery mechanism to undo the effects of misspeculations. We illustrate the potential of speculation to simplify multiprocessor design with three examples. First, we simplify the design of a directory cache coherence protocol by speculatively relying on point-to-point ordering of messages in an adoptively routed interconnection network. Second, we simplify a snooping cache coherence protocol by treating a rare coherence state transition as a misspeculation. Third, we simplify interconnection network design by removing the virtual channels and then recovering from deadlocks when they occur. Experiments with full-system simulation and commercial workloads show that speculation is a viable approach for simplifying system design. Systems can incur as many as ten recoveries per second due to misspeculations without significantly degrading performance, and our speculatively simplified designs incur far fewer recoveries.
  • Keywords
    cache storage; multiprocessing systems; parallel programming; system recovery; adoptively routed interconnection network design; deadlocks; directory cache coherence protocol; efficient recovery mechanism; modern multiprocessor design; point-to-point ordering; rare coherence state transition; snooping cache coherence protocol; virtual channel; Degradation; Dynamic scheduling; Event detection; Hardware; Information science; Multiprocessor interconnection networks; Processor scheduling; Protocols; System recovery; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
  • Print_ISBN
    0-7695-2132-0
  • Type

    conf

  • DOI
    10.1109/IPDPS.2004.1303007
  • Filename
    1303007