Finite Element Modeling of Misalignment in Interconnect Vias

Electrical resistance and hence heat generation in semiconductor chips are becoming more significant issues particularity as generations of silicon devices continue to have smaller features. The resistance of interconnect vias is a significant source of heat generation because of the increasing number of these on chips and increases in via resistance due to reduced size. Finite element modeling of voltage drops and current now through interconnect vias gives information to aid in designing geometry and materials used in forming vias. It can also be used for modeling the thermal distribution in a via and hence the contribution by vias to heating a chip. In this paper we examine the effect of misalignment of the via between the two metal layers M1 and M2 with regard to the interconnect via resistance. The effect of the interface specific contact resistance is examined in particular. Significant misalignment can be tolerated without increasing the via resistance. The heat generation due to electrical current flow in the via materials and interfaces is modelled using the same finite element mesh and software. The output of the electrical analysis is used as the heat generation input for the thermal analysis