A high-efficiency cascaded multilevel class-D amplifier with FPGA based on sliding mode control

A novel switch-mode power amplifier based on a Cascaded multicell multilevel circuit topology is introduced in the paper. The article lays emphasis on the design of the sliding mode controller of a multilevel class-D power amplifier and deduces the sliding mode controller´s parameters. The multilevel class-D power amplifier´s multi-channel PWM gate circuit based on Field Programmable Gate Array (FPGA) is developed. The principle of the phase-shifted PWM control is described, operating these with which gives higher output power and produces an improved output voltage spectrum and significantly lowers output current-ripple. The research results show that this kind of amplifier significantly increases the system bandwidth, provides the system with fast following performance and stability, high efficiency, no matter the system is under resistive load or bridge rectifier load.