DocumentCode
3043529
Title
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture
Author
Sanusi, Azeez ; Wang, Nan ; Bayoumi, Magdy A.
Author_Institution
Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA
fYear
2008
fDate
17-20 Sept. 2008
Firstpage
75
Lastpage
78
Abstract
As technology dives deeper into the submicron, the complexities of systems-on-chip (SoC) increase due to the integration of a large number IP cores on the same silicon die. The network-on-chip paradigm has been widely accepted as a promising solution to the increasing complexity of on-chip communication requirements, with the quality of service network-on-chip (QNoC) being an effective solution when dealing with networks that have varying bounds on latency and throughput for different applications. In this paper, we present a router architecture to provide QoS support based on a simple extension to the router architecture PMCNOC and based on the definition of service classes. Our experiments show that the proposed architecture can meet the quality of service (QoS) requirements of the different service classes while maintaining hardware simplicity.
Keywords
network routing; network-on-chip; quality of service; IP cores; NoC communication architecture; QoS; SoC; onchip communication requirements; pipelined multichannel central caching; quality of service network-on-chip; router architecture; systems-on-chip; Delay; Energy consumption; Hardware; Jitter; Network-on-a-chip; Quality of service; Silicon; System-on-a-chip; Telecommunication traffic; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2008 IEEE International
Conference_Location
Newport Beach, CA
Print_ISBN
978-1-4244-2596-9
Electronic_ISBN
978-1-4244-2597-6
Type
conf
DOI
10.1109/SOCC.2008.4641483
Filename
4641483
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