A 300-mV 36-μW multiphase dual digital clock output generator with self-calibration

A 300 mV 20 MHz-350 MHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90 nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120 ps when delay-locked loop is operating at 40 MHz/300 mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 muW at 40 MHz/300 mV.