Design methodolgy for HD Photo compression algorithm targeting a FPGA

This paper presents a design methodology for implementing the HD photo compression algorithm within a FPGA. The HD photo compression algorithm is comprised of five pipelined functional stages; (transformation, quantization, prediction, scanning, and encoding) some of which can be manipulated to obtain a lower cost and/or higher performance solution. This flexibility enables tailored solutions to be developed for a broader spectrum of applications. An Altera Stratix III FPGA can compress a 56 megapixel image in hundreds of microseconds.