Title :
Unification of obstacle-avoiding rectilinear Steiner tree construction
Author :
Jiang, Iris Hui-Ru ; Lin, Shung-Wei ; Yu, Yen-Ting
Author_Institution :
Dept. of Electron. Eng.&Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu
Abstract :
Multi-layer obstacle-avoiding rectilinear Steiner tree construction is an essential problem in physical design for advanced SoC and nano technologies. This paper unifies obstacle-avoiding rectilinear Steiner tree construction either for single or for multiple routing layers. Experimental results show that our algorithm outperforms the state-of-the-art works for both cases.
Keywords :
collision avoidance; network routing; system-on-chip; trees (mathematics); SoC; multiple routing layers; nano technologies; obstacle-avoiding rectilinear Steiner tree construction; Art; Cost function; Iris; Maintenance engineering; Pins; Routing; Runtime; Steiner trees; Tree graphs;
Conference_Titel :
SOC Conference, 2008 IEEE International
Conference_Location :
Newport Beach, CA
Print_ISBN :
978-1-4244-2596-9
Electronic_ISBN :
978-1-4244-2597-6
DOI :
10.1109/SOCC.2008.4641494