Title :
A 0.5V 25Mpixels/s SVGA 30fps H.264 video decoder chip
Author :
Chen, Jia-Wei ; Chang, Pei-Yao ; Chang, Keng-Jui ; Kuo, Tzu- Yuan ; Hsu, Wei-Han ; Wang, Jinn-Shyan ; Chien, Cheng-An ; Chang, Hsiu-Cheng ; Guo, Jiun-In
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Abstract :
A sub-threshold voltage, high throughput H.264 video decoder design is proposed for portable applications in this paper. To improve the performance for high throughput rate applications, the computational complexity in H.264 video decoding is optimized in the proposed design. To reduce complexity, both a shared adder-based hardware sharing scheme and an advanced data management scheme are presented. Moreover, to reduce power consumption, both a low area sub-threshold voltage SRAM and a high performance sub-threshold voltage CMOS circuit design scheme are presented. Exploiting all the design techniques, the proposed 90nm 0.5V 25Mpixels/s SVGA 30fps H.264 decoder outperforms the 65nm design at 0.5V through a 31× improvement in throughput.
Keywords :
CMOS integrated circuits; SRAM chips; adders; computational complexity; decoding; integrated circuit design; video codecs; video coding; SVGA H.264 video decoder chip; advanced data management scheme; computational complexity; high performance sub-threshold voltage CMOS circuit design scheme; high throughput H.264 video decoder chip design; low area sub-threshold voltage SRAM; power consumption reduction; shared adder-based hardware sharing scheme; size 65 nm; size 90 nm; video codecs; voltage 0.5 V; CMOS integrated circuits; Computer architecture; Decoding; Encoding; Microprocessors; Random access memory; Throughput; CMOS digital integratd circuits; H.264/AVC; Low-power electronics; SRAM chip; Sub-threshold circuit design; Video codecs;
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
DOI :
10.1109/ISICir.2011.6131867
