Title :
Image classifying algorithm and its VLSI implementation based on the directional features
Author :
Wang, Dongfang ; Yu, Ningmei ; Lam, Y.H.Y. ; Zheng, Yuanjin
Author_Institution :
Dept. Electron. Eng., Xi´´an Univ. of Technol., Xi´´an, China
Abstract :
Vector quantization (VQ) is widely used in the field of image coding because of its simple decoding algorithm and high compression rate. But owing to its high complexity of image codeword matching process, it is often limited out of some place requisite of real time. In order to accelerate this process, a novel direction classifying criterion is presented in this paper, it is based on the good image directional selectivity of wavelet transform, and deduced and simplified from the relationship of the coefficients of quadric wavelet transform. This criterion was used to improve the efficiency of codewords matching in VQ algorithm. Simulation results show that, in average, this algorithm can reduce time passing to 38.4% within 1.8% PSNR lost in contrast with the common VQ. At the same time, this criterion is simple and easy to be implemented using VLSI technology, and its pipe-line VLSI architecture can be easily integrated in other image encoding chips due to its regularity and modularity. In this paper, it was integrated into PDVQ chip fabricated with 0.35μm CMOS process, to speed up its image encoding. Test results show that, the PDVQ chip can determine the image direction correctly, and at 3.0V power supply, PDVQ chip can operate steadily under 100MHz, and which can support real-time encoding application for 512×512 gray images at 30 frame/s.
Keywords :
CMOS logic circuits; VLSI; image classification; image coding; image matching; vector quantisation; wavelet transforms; CMOS process; PDVQ chip; VLSI implementation; compression rate; decoding algorithm; direction classifying criterion; directional features; frequency 100 MHz; image classifying algorithm; image codeword matching process; image coding; image directional selectivity; image encoding chips; pipe-line VLSI architecture; quadric wavelet transform; size 0.35 mum; vector quantization; voltage 3 V; Classification algorithms; Computer architecture; Image coding; Vector quantization; Very large scale integration; Wavelet transforms; VLSI; image coding; vector quantization;
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
DOI :
10.1109/ISICir.2011.6131877