DocumentCode
3043979
Title
Designing concurrent checking sorting networks
Author
Kantawala, Kamal ; Tao, D.L.
Author_Institution
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
fYear
1993
fDate
22-24 June 1993
Firstpage
250
Lastpage
259
Abstract
The author´s propose two new concurrent error detection (CED) schemes for a class of sorting networks (SNs), e.g., odd-even transposition, bitonic, and perfect shuffle SNs. They propose a CED scheme by which all errors caused by single faults in a concurrent checking SN can be detected. This scheme is the first one available to use significantly less hardware overhead than duplication without compromising throughput. From this scheme, the authors develop another fault detection scheme which sharply reduces the hardware overhead but still achieves virtually complete fault coverage. In addition, a new design for a checker is provided. This checker is used to check the concurrent checking SN, i.e., the SN as well as itself, during normal operation.
Keywords
error detection; bitonic; checker; concurrent checking sorting networks; concurrent error detection; fault detection scheme; hardware overhead; odd-even transposition; perfect shuffle SNs; virtually complete fault coverage; Circuit faults; Data processing; Fault detection; Fault tolerance; Hardware; Signal processing; Sorting; Throughput; Tin; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
Conference_Location
Toulouse, France
ISSN
0731-3071
Print_ISBN
0-8186-3680-7
Type
conf
DOI
10.1109/FTCS.1993.627328
Filename
627328
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