DocumentCode
3044024
Title
Reconfigurable back propagation based neural network architecture
Author
Wu, Gin-Der ; Zhu, Zhen-Wei ; Lin, Bo-Wei
Author_Institution
Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli, Taiwan
fYear
2011
fDate
12-14 Dec. 2011
Firstpage
67
Lastpage
70
Abstract
Since the topology of neural networks is very crucial to the performance, the reconfigurable ability of the neural network hardware is very important. Therefore, this paper proposes an efficient architecture to implement the reconfigurable back propagation based neural network (BPNN). To further reduce the hardware, this paper adopts the resource sharing method. Finally, Xilinx - ISE is used to synthesize BPNN into the field-programmable gate arrays (FPGA) in experiments.
Keywords
backpropagation; field programmable gate arrays; neural net architecture; reconfigurable architectures; Xilinx-ISE; field-programmable gate arrays; neural network architecture; neural network hardware; reconfigurable ability; reconfigurable back propagation; resource sharing method; Approximation methods; Biological neural networks; Computer architecture; Field programmable gate arrays; Hardware; Neurons; Training; BPNN; FPGA; neural networks; reconfigurable ability;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-61284-863-1
Type
conf
DOI
10.1109/ISICir.2011.6131881
Filename
6131881
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