An efficient lossless embedded compression engine using compacted-FELICS algorithm

The memory bandwidth and capacity have become a critical design issue in display media chip for high-end display applications. In this paper, the lossless embedded compression engine using compacted-FELICS algorithm, which primarily consists of adjusted binary code and Golomb-Rice code, is proposed to handle this scenario. The encoding capability of its VLSI architecture can achieve Full-HD 1080p@60Hz. The prototype chip is implemented by TSMC 0.18-um with Artisan cell library, and its core size is 0.98 mm x 0.97 mm.