Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes

Author

Kosakowski, Martin ; Wittmann, Reimund ; Schardein, Werner

Author_Institution

Nokia Res. Center, Bochum

fYear

2008

fDate

17-20 Sept. 2008

Firstpage

261

Lastpage

266

Abstract

Behavioural modelling and yield optimization of resistor string based (potentiometer) digital-to-analog-converters (DACs) is presented to improve its reliability and area efficiency with focus on nonideal nanoscale CMOS processes, which suffer from large device tolerances. The optimization potential in terms of yield is analyzed taking systematic and statistical properties into account. Measurements of 4096-step and 16384-step DACs using 65 nm and 180 nm CMOS process show outstanding accuracy performance and excellent matching to simulated circuit performance using the behavioural model. Guidelines for efficient resistor string based DAC-design are presented.

Keywords

CMOS integrated circuits; circuit reliability; digital-analogue conversion; logic design; statistical analysis; DAC architectures; device tolerances; digital-to-analog-converters; nanoscale CMOS processes; resistor string based DAC-design; size 180 nm; size 65 nm; statistical averaging based linearity optimization; CMOS process; CMOS technology; Guidelines; Linearity; Mathematical model; Nanoscale devices; Potentiometers; Resistors; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2008 IEEE International

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4244-2596-9

Electronic_ISBN

978-1-4244-2597-6

Type

conf

DOI

10.1109/SOCC.2008.4641524

Filename

4641524