Title :
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor
Author :
Silva-Filho, A.G. ; Lima, S.M.L.
Author_Institution :
Dept. of Comput. & Syst., Univ. of Pernambuco (POLI-UPE), Recife
Abstract :
The memory hierarchy of an embedded system can consume up to 50% of microprocessor system power (Segars, S.,2001). This paper proposes: (i) a design flow to estimate energy consumption and performance using an SoC system based on FPGA, and (ii) an automated architecture exploration mechanism based on parameter variation of a memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 9% of the design space, an energy consumption reduction of about 27% has been achieved, as well as an increase of 10% in the performance of the application.
Keywords :
cache storage; circuit tuning; embedded systems; field programmable gate arrays; microprocessor chips; system-on-chip; FPGA; Mibench; NIOS II processor; SoC system; XiRisc; automated architecture exploration mechanism; cache configuration tuning; embedded system; energy consumption reduction mechanism; memory hierarchy; microprocessor system power consumption; parameter variation; Analytical models; Embedded computing; Embedded system; Energy consumption; Field programmable gate arrays; Logic; Microprocessors; Performance analysis; Space exploration; Space technology;
Conference_Titel :
SOC Conference, 2008 IEEE International
Conference_Location :
Newport Beach, CA
Print_ISBN :
978-1-4244-2596-9
Electronic_ISBN :
978-1-4244-2597-6
DOI :
10.1109/SOCC.2008.4641530
