Low-power, low-offset stacked analog latch using an offset cancellation technique

Author

Tateno, Minehiko ; Date, Hiroki ; Ohhata, Kenichi

Author_Institution

Dept. of Electr. & Electron. Eng., Kagoshima Univ., Kagoshima, Japan

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

140

Lastpage

143

Abstract

In this paper, a low-power, low-offset analog latch is proposed. A stacked analog latch and a novel offset cancellation technique were combined to achieve low-power and low-offset analog latch. Circuit simulations demonstrated that power dissipation could be reduced by 35% in comparison with using a conventional offset cancellation technique. A test chip fabricated by using 180-nm CMOS technology showed that the proposed circuit reduced the standard deviation of the offset voltage from 15.5 to 3.3 mV. Moreover, the proposed circuit could maintain offset low in the range of the input common level from 0.6 to 1.6 V.

Keywords

CMOS integrated circuits; circuit simulation; flip-flops; low-power electronics; CMOS technology; circuit simulations; low-power low-offset stacked analog latch; offset cancellation technique; power dissipation; size 180 nm; test chip; voltage 0.6 V to 1.6 V; voltage 3.3 mV to 15.5 mV; CMOS integrated circuits; Clocks; Latches; Logic gates; Power dissipation; Threshold voltage; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2011 13th International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-61284-863-1

Type

conf

DOI

10.1109/ISICir.2011.6131897

Filename

6131897