Title :
A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards
Author :
Cheng-Hung Lin ; Chun-Yu Chen ; En-Jui Chang ; An-Yeu Wu
Author_Institution :
Dept. of Electr. Eng., Yuan Ze Univ., Jungli, Taiwan
Abstract :
This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems. A contention-free vectorizable dual-standard interleaver is proposed to enhance the hardware utilization. Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems. This chip fabricated in a core area of 3.38 mm2 by 90nm CMOS process is measured at 152 MHz with a power consumption of 148.1 mW and a throughput rate of 186.1 Mbps. This chip achieves a high area efficiency of 0.36 bit/mm2 and a low energy efficiency 0.16 nJ/bit/iteration.
Keywords :
CMOS integrated circuits; Long Term Evolution; VLSI; WiMax; convolutional codes; interleaved codes; turbo codes; CMOS process; LTE standards; VLSI architecture; WiMAX; contention-free vectorizable dual-standard interleaver; convolutional turbo code; frequency 152 MHz; parallel MAP decoding; power 148.1 mW; size 90 nm; turbo decoder chip design; Bit error rate; Decoding; Iterative decoding; Kernel; Parallel processing; Throughput; WiMAX; LTE; Multi-standard; Turbo Decoder; WiMAX;
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
DOI :
10.1109/ISICir.2011.6131904
