• DocumentCode
    3044537
  • Title

    Timing analysis: in search of multiple paradigms

  • Author

    Muller, Frank

  • Author_Institution
    Dept. of Comput. Sci., North Carolina State Univ., Raleigh, NC, USA
  • fYear
    2004
  • fDate
    26-30 April 2004
  • Firstpage
    126
  • Abstract
    Summary form only given. While timing analysis is a vital prerequisite for real-time schedulability tests, prior advances on timing analysis were sometimes incremental in addressing selected new processor features or limited source code annotations to provide safe but tight WCET bounds. In contrast, recent advances in timing analysis including a refreshing set of novel approaches to bound the worst-case execution time (WCET) of real-time tasks. These advances are in search of new methodologies to address the timing analysis problem and approach this problem in a more general manner. Examples are 1) the complexity wall of hardware that causes timing analysis tools to trail behind the curve of microarchitectural innovation, 2) severe restrictions on the knowledge of loop bounds, 3) the inability to analysis large application programs, 4) a lack of capitalizing on opportunities of dynamic scheduler interactions and 5) the challenge in expressing certainty levels of WCET bounds. We give an overview of selected approaches and contribute an initial account on the potential of the contributions for the field. Each of these novel approaches to timing analysis solves one problem in current toolsets. It appears that the diversity of approaches is a valuable asset to the research area. While a particular solution may prove best suitable for some problem, another approach may be required for different problems. Furthermore, many of the recent advances are complementing each other. Some can be used in conjunction to provide additional robustness to hard real-time systems.
  • Keywords
    computational complexity; processor scheduling; real-time systems; timing; real-time schedulability test; real-time system; timing analysis; worst-case execution time; Computer science; Embedded system; Hardware; Microarchitecture; Processor scheduling; Real time systems; System testing; Technological innovation; Timing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
  • Print_ISBN
    0-7695-2132-0
  • Type

    conf

  • DOI
    10.1109/IPDPS.2004.1303090
  • Filename
    1303090