DocumentCode
3044567
Title
Dynamic hardware plugins (DHP): exploiting reconfigurable hardware for high-performance programmable routers
Author
Taylor, David E. ; Turner, Jonathan S. ; Lockwood, John W.
Author_Institution
Appl. Res. Lab., Washington Univ., St. Louis, MO, USA
fYear
2001
fDate
2001
Firstpage
25
Lastpage
34
Abstract
This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. By enabling multiple applications to be dynamically loaded into a single hardware device, the DHP architecture provides a scalable mechanism for implementing high-performance programmable routers. The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. Possible implementations are described as well as the prototype testbed at Washington University in Saint Louis
Keywords
computer networks; field programmable gate arrays; network operating systems; reconfigurable architectures; telecommunication network routing; FPGA; active networking; dynamic hardware plugins; high-performance programmable routers; multiple networking applications; port processor; reconfigurable hardware; scalable mechanism; Application software; Computer architecture; Drives; Fabrics; Hardware; Laboratories; Logic devices; Process control; Reconfigurable logic; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Open Architectures and Network Programming Proceedings, 2001 IEEE
Conference_Location
Anchorage, AK
Print_ISBN
0-7803-7064-3
Type
conf
DOI
10.1109/OPNARC.2001.916836
Filename
916836
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