Power/throughput/area efficient PIM-based reconfigurable array for parallel processing

Author

Purohit, Sohan ; Chalamalasetti, Sai ; Margala, Martin ; Corsonello, Pasquale

Author_Institution

Dept. of Electr. & Comput. Eng, Univ. of Massachusetts Lowell, Lowell, MA

fYear

2008

fDate

17-20 Sept. 2008

Firstpage

375

Lastpage

378

Abstract

This paper presents a PIM-based (Processing-in-Memory) architecture based on new reconfigurable cell data path. The architecture delivers increased power/throughput/area efficiency compared to previous well-known architectures. The investigation of the new reconfigurable cell design was performed in 0.18 and 0.13 micron CMOS technology nodes. Specifications of individual blocks are presented as well as a comparison with existing designs for 8x8 2D DCT application.

Keywords

CMOS memory circuits; discrete cosine transforms; parallel processing; reconfigurable architectures; 2D discrete cosine transforms; CMOS technology; area efficiency; parallel processing; power efficiency; processing-in-memory architecture; reconfigurable cell data path; size 0.13 mum; size 0.18 mum; throughput efficiency; CMOS technology; Centralized control; Circuits; Computer architecture; Parallel processing; Radio control; Random access memory; Read only memory; Reconfigurable architectures; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2008 IEEE International

Conference_Location

Newport Beach, CA

Print_ISBN

978-1-4244-2596-9

Electronic_ISBN

978-1-4244-2597-6

Type

conf

DOI

10.1109/SOCC.2008.4641548

Filename

4641548