Title :
Robust sequential fault testing of iterative logic arrays
Author :
Gizopoulos, D. ; Psarakis, Mihalis ; Paschalis, Antonis
Author_Institution :
Inst. of Inf. & Telecommum., NCSR Demokritos, Athens, Greece
fDate :
27 Apr-1 May 1997
Abstract :
Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs
Keywords :
CMOS logic circuits; fault diagnosis; logic arrays; logic testing; sequential circuits; C-testability; algorithm; cell model; glitch; iterative logic array; linear testability; one-dimensional CMOS ILA; robust sequential fault testing; two-pattern testing; Benchmark testing; CMOS logic circuits; CMOS technology; Delay; Fault detection; Logic arrays; Logic testing; Robustness; Semiconductor device modeling; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600280
