DocumentCode :
3044679
Title :
Flying-Adder on-chip frequency synthesis architecture
Author :
Liming Xiu, Liming
fYear :
2008
fDate :
17-20 Sept. 2008
Firstpage :
389
Lastpage :
389
Abstract :
The construction of on-chip clock circuitry has great impact on both system performance and chip implementation cost. Among the many aspects of the clock circuitry, the most important one is its capability of producing frequencies. Flying-adder frequency synthesis architecture, one of the latest developments in clock generation circuitry, is such a circuit-level enabler which can help circuit designers and system engineers to create better-performance and/or lower-cost systems. With this technique, many system and software level issues can be investigated from new directions. Compared to the conventional techniques, this method is capable of generating much more frequencies. Furthermore, it provides great controllability to software so that software programmers have the flexibility of creating novel approaches to differentiate their products from the competitorspsila. In this tutorial, the flying-adder architecture will be first introduced. Then, several real systems are used to demonstrate the power of this new frequency synthesis technique.
Keywords :
adders; clocks; circuit designers; circuit-level enabler; clock circuitry; clock generation circuitry; flying-adder onchip frequency synthesis architecture; frequency synthesis technique; onchip clock circuitry; software programmers; Circuit synthesis; Clocks; Computer architecture; Costs; Design engineering; Frequency synthesizers; Software systems; System performance; System-on-a-chip; Systems engineering and theory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2008 IEEE International
Conference_Location :
Newport Beach, CA
Print_ISBN :
978-1-4244-2596-9
Electronic_ISBN :
978-1-4244-2597-6
Type :
conf
DOI :
10.1109/SOCC.2008.4641551
Filename :
4641551
Link To Document :
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