Timing reconfigurable microarchitectures for power efficiency

Summary form only given. Modern microprocessors are designed with a fixed set of microarchitected resources. On the other hand, program resource requirements are known to vary across programs and even within a program as it goes through different phases of execution. This mismatch between the design and program requirements often leads to suboptimal power and/or performance. We present an adaptive microarchitecture that tailors itself dynamically to match changing program requirements. The goal of adaptation in this work is to achieve power efficiency without suffering significant performance degradation. The microarchitecture employs four multiconfiguration units nstruction cache, data cache, unified L2 cache and branch predictor along with light weight profiling hardware and sophisticated tuning algorithms. The profiling hardware collects working set signatures using a simple hash function and sparse sampling in order to reduce profiling hardware complexity. The tuning algorithms use these signatures to accurately detect program phase changes and decouple the tuning of each unit using a novel technique. Detailed simulations show that the best performing algorithm achieves subthreshold leakage power reductions as high as 76% for instruction cache, 46% for data cache, 63% for L2 cache and 73% for the branch predictor in the benchmarks studied. On average, the algorithm leads to 1.1% performance degradation while achieving 44%, 17%, 19%, and 28% reduction in subthreshold leakage power for instruction cache, data cache, L2 cache and branch predictor, respectively.