A reconfigurable tag computation architecture for terabit packet scheduling

Summary form only given. We present the hardware architecture and implementation of a reconfigurable tag computation circuit for terabit packet scheduling for future QoS aware core routers. The presented implementation provides a platform for a runtime configurable scheduling architecture that is able to reallocate bandwidth on the fly. The system is implemented using FPGA technology and provides extended programmability to adapt the tag computation to a range of custom packet scheduling policies. The hardware architecture is parallel and pipelined enabling an aggregated throughput rate of 175 million tag computations per second, easily out performing current QoS router solutions. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented.