Design and optimzation of high precision CMOS voltage reference using Taguchi orthogonal array technique

A CMOS voltage reference, which is based on the weighted compensation of thermal voltage and threshold voltage temperature variations is presented. Subthreshold NMOS transistors and resistive divider configuration are used to achieve reference voltage with low temperature coefficient. Taguchi orthogonal array technique is presented to optimize the circuit to attain precise reference voltage with high PSRR. The proposed voltage reference circuit is analyzed theoretically and compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology. The minimum supply voltage is 1.2 V. A temperature coefficient of 3.6 ppm/°C is achieved with line sensitivity of 0.01%/V. Moreover, PSRR at 100 Hz and 1 MHZ is -100.8 dB and -31.2 dB respectively.