Real-time configuration code decompression for dynamic FPGA self-reconfiguration

Summary form only given. Xilinx Virtex FPGAs have the possibility of dynamical partial run-time reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution of parts in reconfiguration memory, the amount of necessary memory increases. The sum of memory amount which has to be provided for the configuration data is not negligible. This fact suggests the investigation of compressing data before they are stored in memory modules of a system. The compressed bitstream data has to be decompressed before transferring it to the FPGA. We show an approach of compressing configuration data at design time and decompressing them with a hardware module implemented on FPGA while run-time.