A new approach for testing artificial neural networks

Author

Fleischer, Curtis A. ; Belfore, Lee A., II

Author_Institution

Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA

fYear

1997

fDate

27 Apr-1 May 1997

Firstpage

245

Lastpage

250

Abstract

This paper presents progress on a new and novel testing approach for detecting interconnection deletion faults in electronic implementations of artificial neural networks (ANNs). The testing approach is based on an unusual transient behavior manifested by faulted ANNs showing better apparent performance than fault-free ANNs, when neurons are operated with low activation function gains. The result presented in this paper improves on prior results by requiring fewer test patterns

Keywords

VLSI; automatic testing; built-in self test; integrated circuit testing; neural chips; activation function gains; artificial neural networks; faulted ANN; interconnection deletion faults; testing; transient behavior; Artificial neural networks; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Electronic equipment testing; Integrated circuit interconnections; Manufacturing; Neurons;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1997., 15th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-7810-0

Type

conf

DOI

10.1109/VTEST.1997.600282

Filename

600282

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3045004