DocumentCode :
3045109
Title :
An 80-dB SNR 4th-order discrete-time sigma-delta modulator
Author :
Kwon, Chan-Keun ; Jeong, Chan-Hui ; Min, Young-Jae ; Jung, Young-Mok ; Kim, Soo-Won
Author_Institution :
Dept. of Nano-Semicond. Eng., Korea Univ., Seoul, South Korea
fYear :
2011
fDate :
12-14 Dec. 2011
Firstpage :
230
Lastpage :
233
Abstract :
This paper presents a 4th-order single-bit DT ΔΣ modulator for audio applications. To achieve higher signal-to-noise ratio (SNR), the compensation capacitors in the input of a comparator are exploited to reduce the metastability of a comparator. The proposed modulator has been fabricated in a quantizer level 0.18-μm CMOS process. Measurements show a SNR of 80.27 dB and a signal-to-noise and distortion ratio (SNDR) of 77.58 dB over a 40-kHz signal bandwidth with a sampling clock frequency of 10.24 MHz. A total power consumption including a clock generator is 340 μW with a 1.8-V supply voltage.
Keywords :
CMOS digital integrated circuits; sigma-delta modulation; CMOS process; SNDR; SNR 4th-order discrete-time sigma-delta modulator; audio applications; bandwidth 40 kHz; clock generator; compensation capacitors; frequency 10.24 MHz; power 340 muW; quantizer level; sampling clock frequency; signal-to-noise and distortion ratio; single-bit DT ΔΣ modulator; size 0.18 mum; total power consumption; voltage 1.8 V; Bandwidth; Capacitors; Clocks; Modulation; Power demand; Signal to noise ratio; Analog-to-digital converter; comparator-metastability; compensation capacitor; discrete-time ΔΣ modulator;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits (ISIC), 2011 13th International Symposium on
Conference_Location :
Singapore
Print_ISBN :
978-1-61284-863-1
Type :
conf
DOI :
10.1109/ISICir.2011.6131938
Filename :
6131938
Link To Document :
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