RECASTER: synthesis of fault-tolerant embedded systems based on dynamically reconfigurable FPGAs

Summary form only given. We present a fault-tolerant embedded system design methodology that uses dynamically reconfigurable FPGAs as spares for several dedicated hardware components. The key advantage is the reduction of area or cost as compared to dedicated spares. During normal operation, each FPGA is dynamically reconfigured with system tasks and can replace any of them if a fault is detected. For a specified coverage, i.e., system tasks that might be affected by a single fault, our algorithm allocates a set of FPGAs and determines schedules, including task executions and FPGA reconfigurations, that provide the required redundancy while satisfying deadlines and minimizing either area or cost. For each task requiring simple redundancy, the algorithm also determines a schedule in which an FPGA replaces this task. Our experimental results indicate that, with a smaller area and cost, this collective redundancy based on dynamically reconfigurable FPGAs allows system recovery from a larger number of single faults, each affecting one task, as compared to the conventional spare approach.